1. Field of Invention
The present invention relates to designing of integrated circuits and more particularly to simulating the behavior of power domains in the IC design process.
2. Description of Related Art
There is a growing need for enhanced power management capability in electronic devices, especially in battery-operated portable wireless devices such as cell phones, for example. Power management typically involves minimizing overall power consumption among different device functions. The intricacies of power management increase with the number and complexity of device functions.
Power management capabilities typically are built into a circuit design. Techniques to design-in power consumption management in an integrated circuit (IC) design include minimization of leakage power dissipation, design of efficient packaging and cooling systems and verification of functionality or power shut-off sequences early in the IC design process. Efficient power consumption may become an integrated circuit design criterion that is almost as critical as timing and area, particularly for portable consumer electronics, for example.
Modern electronic design typically is performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates a high level behavior description of an IC device using a high-level hardware design language (HDL). Typically, an HDL is used to express a register transfer level (RTL) description of a design that describes a circuit in terms of a sequence of transfers of data. The word ‘register’ refers to the fact that in a circuit undergoing design, such transfers ultimately will occur between storage elements such as registers, for example. VHDL and Verilog, are examples of some of the more popular HDLs. An RTL description, for instance, may describe a circuit as a collection of registers, Boolean equations, control logic such as “if-then-else” statements as well as complex event sequences. An RTL description may describe functionality of a set of interconnected modules of varied complexity, from simple logic gates to full blown multipliers, for example. An RTL specification provides instructions to EDA systems, for example, to produce a gate-level netlist and then, through additional design implementation stages, a physical design. The design process typically involves both functional design and verification and physical design and verification.
In the past, power optimization techniques typically have been applied at the physical implementation phase of the design. Certain advanced power management techniques such as multiple power domains with power shut-off (PSO) methodology ordinarily have been implemented at the physical level (i.e., post synthesis). These advanced power management design techniques can significantly influence the design intent. Yet, ordinarily, intended power management behavior is not readily captured in an RTL description of a circuit design. This can result in a gap in the RTL to Graphic Design System II (GDSII) implementation and verification flow where the original RTL is no longer reliable and cannot be used to verify the final netlist implementation containing the advanced power management techniques. In other words, if an RTL description does not adequately encompass power management requirements, it is not readily feasible to check a final netlist against its original corresponding RTL design, since the addition of power management circuitry, during physical implementation, for example, may change the design in ways that make the RTL description an unreliable indicator of whether the final netlist actually comports with original design intent.
In addition, these specialized power management techniques at the physical implementation stage generally cannot be used by EDA tools at other stages of the design process, and therefore, cannot be used by EDA tools at an earlier RTL or gate level stage of the IC design process to perform, for example, functional verification. One reason this is important is that verification of low power designs only at the physical implementation stage of the design process may not capture all potential design flaws within the IC, particularly potential sequence-related problems for power modes that would be more aptly tested at a functional stage of the IC design process.
Furthermore, incorporation of power shut off capability into a functional design as a power saving mechanism, for example, can influence functional behavior of a circuit design. For instance, an original design expressed in an HDL implicitly assumes an uninterrupted source of power. However, the addition of a power-shut-off capability to select portions of a design may undermine that assumption since the shut-off of power in one part of a circuit design may impact the function of other portions of the design
With the ever increasing demands for low power electronics, design and verification EDA tools have attempted to include power in their design and verification offerings. However, the concept of power is not an intrinsic part of the underlying semantics of Hardware Description Languages (HDL) such as Verilog and VHDL. This can cause discrepencies between the modeled behaviour and the corresponding behaviour of real hardware. In particular, simulating the behavior of register values in power domain systems may be inaccurate if the effects of power cycling (e.g., register corruption) are not adequately handled. Thus, there is a need for improved simulations for power domain systems.